Today's System-on-chip (SOC) integrated circuit designs need to comprehend new technology features from industry groups, such as the Peripheral Component Interconnect—Special Interest Group (PCI-SIG) while concurrently sharing the intellectual property (IP) with other groups within a company, when the actual IP feature definition is not fully defined.
As demand for I/O performance increases, many designs use adaptive equalization schemes with feedback controls to self-correct. While creative, such designs of that type are so finely tuned that when the silicon of the design is finally available, there is a risk that the process design target has changed, often rendering less desirable analog behavior and thereby forcing new iterations of the design in the silicon. Corrections to any analog circuitry add delays for time to market as those changes require a repeat of the design-to-process steps.
Observations have been noted that when the new technology architecture definition for high speed I/O are not completely encompassed in the design before the manufacturing specifications for the design are sent to the fabrication facility, lengthy debug efforts can occur for multiple teams. Designing to specifications defined outside the company make it challenging to discern if ones design completely encompasses all features. Pressure to quickly deliver new technology, while the architecture definition is incomplete unintentionally causes this result. The combination of these problems creates costly delays in product introduction of cutting edge technology.
High-speed interfaces such as PCI Express and wireless communication IP require hand-shaking mechanisms to ensure proper packet passing has occurred. Identifying the correct I/O settings for each device is a complex training exercise. Today, the I/O design consists largely of adaptive algorithms on-die, with the algorithms being highly dependent on transistor process characteristics available during design. This adaptive equalization circuitry is finely tuned and can be sensitive to process variations. Adjustments and ranges for the I/O signaling to be operational across various channel types can be limited. Typically, there are many knobs to adjust, yet unexpected channel characteristics may lead to a product requirement process that includes a hunt to identify the correct “knobs” to adjust for signal optimization, while the ability to adjust training transitions via a finite state machine (FSM) control is not available at the platform level, as the FSM behavior is fixed in silicon.
Interfacing a high-speed I/O device with another high-speed I/O device is less problematic when the system designer controls both devices, since parameter adjustments on both sides of the channel can be controlled. However, to interface a high-speed I/O device with externally designed circuitry is very challenging, since state machine control is locked in silicon and depends heavily on adaptive equalization algorithms. The finite state machines work in concert with signals from the receive logic that collect the transmit logic data fields. Some software interaction is also generally provided to ensure traffic is controlled while equalization is underway.